1. Field of the Invention
The present invention relates to a method for programming a non-volatile memory device, and more particularly, to a method for programming a NAND-type flash memory device using a bulk bias.
2. Description of the Related Art
Information stored in a non-volatile memory cell, a type of semiconductor memory device, is not erased even if power is not supplied. Accordingly, non-volatile memory devices are widely used in computers and memory cards.
Since it is easier to increase the integration degree of a NAND-type flash memory device rather than that of a NOR-type flash memory device in a non-volatile memory device, a NAND-type flash memory device is widely used in a highly integrated flash memory device.
FIG. 1 is a plan view showing part of a cell array region of a general NAND-type flash memory device. FIG. 2 is an equivalent circuit diagram showing the cell array region of FIG. 1.
Referring to FIGS. 1 and 2, active regions 1 are parallel to each other. A string selection line SSL, a plurality of word lines WL1, WL2, . . . , WLn, and a ground selection line GSL which cross the active regions 1 are parallel to one another. Contacts CT for exposing the active regions are positioned in the active regions 1 adjacent to the string selection line SSL. Bit lines BL1 and BL2 electrically connected to the active regions 1 through the contacts CT pass over the respective active regions 1. Also, the active regions 1 adjacent to the ground selection line GSL are extended to the direction parallel to the ground selection line GSL to thereby operate as a common source line (CSL). String selection transistor portions SST1 and SST2 comprised of the string selection transistors are formed where the string selection line SSL crosses the respective active regions 1. Cell transistor portions CT1 and CT2 comprised of a plurality of cell transistors are formed where the respective word lines WL1, WL2, . . . , WLn cross the respective active regions 1. Also, ground selection transistor portions GST1 and GST2 comprised of ground selection transistors are formed where the ground selection line GSL crosses the respective active regions 1.
Each cell transistor is comprised of a tunnel oxide film, a floating gate FG, an inter-poly dielectric layer, and a word line which operates as a control gate electrode, sequentially stacked on the active region 1. Here, the floating gates FG of the respective cell transistors are formed to be separate from each other. As shown in FIG. 1, the string selection transistor, the plurality of cell transistors, and the ground selection transistor, which are serially arranged on the active region 1 comprise one string. Also, the respective cell transistors, the respective string selection transistors, and the respective ground selection transistors are formed as NMOS transistors and are formed in a bulk region such as a P-well region.
FIG. 3 shows voltage waveforms for explaining a method for programming a cell A among a plurality of memory cells constructing the general NAND-type flash memory device shown in FIGS. 1 and 2.
Referring to FIG. 3, the moment a power supply voltage Vcc is applied for a precharge time Tpc to the first bit line BL1 serially connected to a first string including the cell A to be programmed, a pass voltage Vpass and a programming voltage Vpgm are sequentially applied to the second word line WL2 corresponding to the control gate electrode of the selected cell A for the precharge time Tpc and a programming time Tpgm, respectively. The power supply voltage Vcc is continuously applied to the string selection line SSL and the second bit line BL2 serially connected to a second string parallel to the first string for the precharge time Tpc and a programming time Tpgm. A pass voltage Vpass is applied to non-selected word lines WLns, i.e., the first word line WL1 and the third word line WL3 through the nth word line WLn for the precharge time Tpc and the programming time Tpgm. Also, 0 volts is applied to the ground selection line GSL, the common source line CSL, and the bulk region.
When predetermined voltages are applied to the respective control lines in order to program the selected cell A as mentioned above, the channel region of the selected cell A and the channel regions of the non-selected cells are precharged for the precharge time Tpc to a voltage close to the power supply voltage Vcc. However, charges precharged in the channel region of the selected cell A are discharged through the first bit line BL1 which falls down to a ground potential for the programming time Tpgm. Accordingly, 0 volts are induced to the channel region of the selected cell A. As a result, the selected cell A is programmed by the programming voltage Vpgm applied to the second word line WL2 and the channel voltage induced to 0 volts.
Meanwhile, the channel regions of the memory cells constructing the second string are electrically isolated from the second bit line BL2 and the common source line CSL for the program time Tpgm, to thereby be floated. Therefore, a voltage increased by the programming voltage Vpgm applied to the second word line WL2 is induced in the channel region of a non-selected cell B which shares the second word line WL2 with the selected cell A. Accordingly, the non-selected cell B is not programmed. At this time, a voltage Vch induced in the channel region of the non-selected cell B can be represented by Equation 1 from FIG. 4 which is a sectional view taken along the line PPxe2x80x2 of FIG. 1 and FIG. 5 which is an equivalent circuit diagram of the non-selected cell B of FIG. 4. Here, a bulk voltage Vb applied to a bulk region 10 of FIG. 4 is 0 volts.
Vch={Ctot÷(Ctot+Cch)}xc3x97Vpgmxe2x80x83xe2x80x83(b 1)
wherein, Ctot is the total capacitance of an inter-poly dielectric layer capacitance Cipo and a tunnel oxide film capacitance Ctox, serially connected to each other. Cch is a depletion capacitance formed in the channel region. The inter-poly dielectric layer capacitance Cipo represents the capacitance of an inter-polysilicon dielectric layer IPO interposed between the floating gate FG and the second word line WL2 of FIG. 4. The tunnel oxide film capacitance Ctox represents the capacitance of a tunnel oxide film Tox interposed between the floating gate FG and the bulk region 10 of FIG. 4.
Referring to FIG. 4 again, a field oxide film Fox operates as an isolation film between the selected cell A and the non-selected cell B. Therefore, a parasitic field transistor is formed between the selected cell A and the non-selected cell B. There is a high probability that the parasitic field transistor is turned on as the channel voltage Vch of the non-selected cell B is higher when the selected cell A is programmed. In addition, it is easier for the parasitic field transistor to turn on as the thickness and the width of the field oxide film Fox are reduced. Accordingly, when the parasitic field transistor is turned on, since undesired leakage current IL flows from the channel region of the non-selected cell B to the channel region of the selected cell A through the surface of the bulk region 10 under the field oxide film Fox, the channel voltage Vch of the non-selected cell B is lowered. As a result, the non-selected cell B is programmed.
As mentioned above, according to the conventional technology, the non-selected cell may be programmed since the parasitic field transistor between the selected cell and the non-selected cell is easily turned on. In particular, when the width and the thickness of the field oxide film are reduced in order to realize a highly integrated NAND-type flash memory device, the non-selected cell is much more easily programmed.
It is an objective of the present invention to provide a method for programming a NAND-type flash memory device by which it is possible to prevent a non-selected cell from being programmed though the thickness and the width of a field oxide film are reduced.
To achieve the above objective, there is provided a method for programming a NAND-type flash memory device having a plurality of strings two-dimensionally arranged in a bulk area of a first conductivity type and a plurality of bitlines arranged in parallel on the plurality of strings, comprising applying a bulk bias corresponding to a reverse bias to the bulk area of the first conductivity type, selecting at least one bitline among the plurality of bitlines, selecting at least one string among the plurality of strings connected to at least one selected bitline in parallel, and programming at least one cell among the plurality of cells constructing the selected string.
The bulk area of the first conductivity type is preferably a p-type semiconductor substrate or a p-type well. Also, the respective strings are comprised of a string selection transistor portion, a cell transistor portion, and a ground selection transistor portion, which are sequentially and serially connected to one another. The string selection transistor portion and the ground selection transistor portion are respectively comprised of at least one NMOS transistor. The cell transistor portion is comprised of a plurality of cell transistors which are serially connected to one another. Each cell transistor has a gate structure in which a tunnel oxide film, a floating gate, an inter-poly dielectric layer, and a control gate electrode are sequentially stacked on the bulk area of the first conductivity type. One cell transistor corresponds to one cell. The source area of the NMOS transistor comprising the ground selection transistor portion of each string, i.e., the source area of the ground selection transistor, is connected to a common source line. The drain area of the NMOS transistor comprising the string selection transistor portion, i.e., the drain area of the string selection transistor, is connected to a bitline. Also, the control gate electrode of each cell transistor is connected to a wordline. The bulk area of the first conductivity type is connected to a bulk line. The string selection transistor portion is controlled by at least one string selection line. The ground selection transistor portion is controlled by at least one ground selection line. To be more specific, the gate electrode of the string selection transistor is connected to the string selection line, and the gate electrode of the ground selection transistor is connected to the ground selection line.
The selecting of at least one bitline among the plurality of bitlines is performed by applying a ground voltage or a pulse voltage having a voltage level the same as that of a power supply voltage, for a predetermined time such as a precharge time, to the bitline connected to a string including at least one selected cell to be programmed. At this time, a program inhibition voltage Vpi, preferably, a power supply voltage Vcc is applied to non-selected bitlines among the plurality of bitlines.
Also, the selecting of at least one string is performed by turning on the string selection transistor portion of the string including the selected cell and turning off the ground selection transistor portion of the string including the selected cell. At this time, a ground voltage is applied to the common source line connected to the turned off ground selection transistor portion. When the string selection transistor portion is comprised of one string selection transistor formed of the NMOS transistor, it is possible to turn on the string selection transistor portion by applying the power voltage to the string selection line connected to the gate electrode of the string selection transistor. Also, when the ground selection transistor portion is comprised of one ground selection transistor formed of the NMOS transistor, it is possible to turn off the ground selection transistor portion by applying the ground voltage to the ground selection line connected to the gate electrode of the ground selection transistor.
Also, in the selecting of at least one cell and programming it, a wordline connected to the control gate electrode of the cell to be programmed is selected from among a plurality of wordlines for controlling the cell transistor portion constituting the selected string, and a programming voltage Vpgm, for example, a high voltage of about 18 volts to 20 volts is applied to the selected wordline. At this time, it is preferable that a voltage higher than the program inhibition voltage Vpi and lower than the programming voltage Vpgm, for example, a pass voltage of about 10 volts to 12 volts is applied to the non-selected wordlines excluding the selected wordline.
It is preferable that the bulk bias applied to the bulk area of the first conductivity type, i.e., the p-type semiconductor substrate or the p-type well is xe2x88x921 volts to xe2x88x922 volts.